In a TV game machine for household use, a personal computer or in a graphics computer, a picture processing apparatus for generating data of a picture outputted and displayed on a TV receiver, monitor receiver, cathode ray tube (CRT) or on a display device, that is display output picture data, is constructed as the combination of a general-purpose memory chip, a central processing unit (CPU) or other processing chips. High-speed processing is enabled by providing a dedicated drawing device between the CPU and a frame buffer.
Specifically, with the above picture processing apparatus, the CPU does not access the frame buffer directly in generating a picture. Instead, the CPU performs geometric processing operations, such as coordinate transformation, clipping or light source calculations and formulates drawing commands for defining a three-dimensional model for drawing a three-dimensional picture as a combination of triangular or quadrangular basic unit figures (polygons) to send the drawing commands over an external bus to the drawing device. For example, for displaying a three-dimensional object, the latter is dissolved into plural polygons and drawing commands associated with the respective polygons are transmitted from the CPU to the drawing device, which then interprets the drawing commands sent from the CPU to the drawing device and calculates the colors of all pixels making up the polygons and the Z-values from the Z-value specifying the color data and depth of apices. The drawing device then performs rendering processing of writing the pixel data in the frame buffer to delineate a figure on the frame buffer. Meanwhile, the Z-value is the information specifying the distance along the depth from the viewing point.
For example, if a three-dimensional object is displayed on the picture generating device, the object is dissolved into plural polygons and the drawing command corresponding to the polygons is transferred from the CPU to the drawing device. For displaying the object more realistically, a technique known as texture mapping or mip mapping is used. There is also known a technique of converting color data of a picture via a color lookup table (CLUT) holding on memory the color conversion data for varying the display colors.
The texture mapping is a technique of bonding a two-dimensional picture (picture pattern), separately provided as a texture source picture, that is a texture pattern, on the surface of a polygon constituting an object. The mip mapping is among texture mapping techniques of interpolating pixel data so that, on approaching to or receding away from a three-dimensional model, the picture pattern bonded to the polygon will not depart from spontaneity.
In a calculation processing system constituted by combining general-purpose memory chips, CPU or other calculation chips, such as TV game machines for household use or personal computers, the memory operating speed or the performance of the external bus is not improved as compared to improvement in the operating frequency of calculation chips or circuit size, such that the external bus proves to be a bottleneck. The memory bus system having a large data transfer volume is generally high in latency and exhibits high performance in large-capacity burst transfer. However, the performance of the memory bus system is not exhibited for a small-capacity random transfer, such as in ordinary CPU accessing.
If a pre-fixed packet, such as a command packet, is used, efficient transfer can be achieved by exploiting a direct memory access controller (DMAC). However, the multifarious algorithm cannot be coped with thus giving rise to redundancy.
The CPU commands are consumed in the packet format and reformat thus lowering the efficiency. If the system has a cache, long packets sufficient to accommodate the packet length cannot be set, such that the burst is usually set to four words and hence the performance of the memory system of the larger data transfer volume cannot be displayed.
In view of the above-described status of the prior art, the present invention has the following objects:
Specifically, an object of the present invention is to reduce the above-mentioned bottleneck in the picture processing apparatus combined from the general-purpose memory chip, CPU and the lie calculation chip.
Another object of the present invention is to provide a picture processing apparatus and a picture processing method for raising the data transfer efficiency.
A further object of the present invention is to provide a picture processing apparatus and a picture processing method for raising the data efficiency on a memory.
A further object of the present invention is to provide a picture processing apparatus and a picture processing method for raising the efficiency in packet data development and packaging efficiency.
A further object of the present invention is to provide a picture processing apparatus and a picture processing method for affording freedom to the packet form.
A still another object of the present invention is to provide a picture processing apparatus and a picture processing method for enabling burst transfer suited to the packet form.